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MiCOM P632
Timers and Tripping Logic
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MiCOM P632
Timers and Tripping Logic
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Associated timer stages are started when a startup criterion is met.
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The signal CBF_1: Trip signal t1 will be issued if the startup criterion is still present when the time delay, set at timer stage CBF_1: t1 3p, has elapsed. The output command from this timer stage is intended for a second CB trip coil. |
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The signal CBF_1: Trip signal t2 will be issued if the startup criterion is still present when the time delay, set at timer stage CBF_1: t2, has elapsed. The output command from this timer stage is intended for a backup circuit breaker or protection system. |
These trip signals will be issued as long as the startup criteria are met.
Should a loss of gas pressure occur in the de-arcing chambers of installed type SF6 circuit breakers then all surrounding circuit breakers must be immediately tripped without waiting for a reaction from the damaged switch. In case of an external CB_ 1 fault the elapsing of timer stage t2 may be interrupted by a signal to the binary signal input appropriately configured at CBF_1: CB faulty EXT.
