MiCOM P632
Programmable Logic (Function Groups LOGIC and LOG_2)

Programmable (or user-configurable) logic enables the user to link binary signals within a framework of Boolean equations.

Two function groups for programmable logic are available, that can be used independently of each other. There are only two differences between these two function groups:

LOGIC offers 32 logical equations.

LOG_2 offers only 4 logical equations.

On the other hand, LOG_2 features long-term timers.

For example for output 1:

LOGIC: Time t1 output 1 and LOGIC: Time t2 output 1: settable from 0 to 600 s.

LOG_2: Time t1 output 1 and LOG_2: Time t2 output 1: settable from 0 to 60,000 s.

Hint

The following description concentrates on the function group LOGIC. Where applicable, any differences to LOG_2 are mentioned.

Binary signals in the P632 may be linked by logical “OR” or “AND” operations with the option of additional NOT operations by setting LOGIC: Fct.assignm. outp. 1 (or LOGIC: Fct.assignm. outp. 2 to LOGIC: Fct.assignm. outp.32, or LOG_2: Fct.assignm. outp. 1 to LOG_2: Fct.assignm. outp. 4). The Boolean equations need to be defined without the use of brackets. The following rule applies to the operators: “NOT” before “AND” before “OR”.

A maximum of 32 elements can be processed in one Boolean equation. In addition to the signals generated by the P632, initial conditions for governing the equations can be set using setting parameters, through binary signal inputs, or through the serial interfaces.

Logical operations of the function group LOGIC can be controlled through the binary signal inputs in different ways.

The binary input signals LOGIC: Input 1 EXT (or LOGIC: Input 2 EXT, …, LOGIC: Input 40 EXT) have an updating function, whereas the input signals LOGIC: Set 1 EXT (or LOGIC: Set 2 EXT, …, LOGIC: Set 8 EXT) are latched. The logic can only be controlled from the binary signal inputs configured for LOGIC: Set 1 EXT if the corresponding reset input LOGIC: Reset 1 EXT) has been configured for a binary signal input. If only one or neither of the two functions is configured, then this is interpreted as “Logic externally set”. If the input signals of the two binary signal inputs are implausible (such as when they both have a logic value of “1”), then the last plausible state remains stored in memory. (For LOG_2, there are no such parameters for assigning binary input signals.)

graphics/symbols/Warning.png WARNING

When using the programmable logic, the user must carry out a functional type test to conform with the requirements of the relevant protection/control application. In particular, it is necessary to verify that the requirements for the implementation of logic linking (by setting) as well as the time performance during startup of the P632, during operation and when there is a fault (blocking of the P632) are fulfilled.

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Fig. 3-176: Control of logic operations via setting parameters or stored input signals. (The logic does not apply to LOG_2.)

The LOGIC: Trigger 1 signal is a “triggering function” that causes a 100 ms pulse to be issued.

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Fig. 3-177: Setting options for programmable logic, function group LOGIC (shown here for output 1).

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Fig. 3-178: Setting options for programmable logic, function group LOG_2 (shown here for output 1).

The output signal of an equation can be fed into a further, higher order, equation as an input signal thus creating a sequence of interlinked Boolean equations. The equations are processed in the sequence defined by the order of each equation. It should be noted that in the case of overlapping equations, the result is provided by the equation with the highest order.

The output signal of each equation is fed to a separate timer stage with two timer elements and a choice of operating modes. This offers the possibility of assigning a freely configurable time characteristic to the output signal of each Boolean equation. In the Minimum time operating mode, the setting of timer stage t2 has no effect. The following diagrams (Fig. 3-179 to Fig. 3-183) show the time characteristics for the various timer stage operating modes.

Hint

If the P632 is switched to offline the equations are not processed and all outputs are set to the “0” logic level.

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Fig. 3-179: Operating mode 1: Pickup/reset delay (Oper./releas.delay). (This diagram is also valid for LOG_2, if the signal parameters are replaced by the corresponding ones from LOG_2 .)

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Fig. 3-180: Operating mode 2: Pulse, delayed pickup (Oper.del./puls.dur.). (This diagram is also valid for LOG_2, if the signal parameters are replaced by the corresponding ones from LOG_2 .)

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Fig. 3-181: Operating mode 3: Pickup/reset delay, retriggerable (Op./rel.delay,retrig). (This diagram is also valid for LOG_2, if the signal parameters are replaced by the corresponding ones from LOG_2 .)

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Fig. 3-182: Operating mode 4: Pulse, delayed pickup, retriggerable (Op.del./puls.dur.,rt). (This diagram is also valid for LOG_2, if the signal parameters are replaced by the corresponding ones from LOG_2 .)

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Fig. 3-183: Operating mode 5: Minimum time (Minimum time). (This diagram is also valid for LOG_2, if the signal parameters are replaced by the corresponding ones from LOG_2 .)

Through appropriate configuration, it is possible to assign the function of a binary input signal to each output of a logic operation. The output of the logic operation then has the same effect as if the binary signal input to which this function has been assigned were triggered.

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Fig. 3-184: Signal assignment to outputs of Boolean equations. (This diagram is also valid for LOG_2, if the parameters from LOGIC are replaced by the corresponding ones from LOG_2 .)